Master Thesis in Virtual Prototyping and Verification

We develop and manufacture semiconductors, sensors, and control units for automotive applications. Complex Systems-on-Chip (SoC) often contain one or more on-chip processors that run software tasks. Virtual Prototypes can be used for efficient pre- and post-silicon software development enabling earlier and more flexible verification as well as software development. During your master thesis you will focus on achieving a flexible and configurable verification approach to speed-up verification of digital design representation at different levels of abstraction and to construct a scheme to classify the test cases within the scope. Quantitative and qualitative metrics will be used to demonstrate the effectiveness of the implemented verification approach. You will learn modern approaches to efficiently develop and integrate virtual prototypes. Furthermore, you will also get familiar with cross-verification of SoC designs in unified verification methodology.